1. Field of the Invention
The present invention relates to a master-slice type semiconductor integrated circuit device and, more particularly, to a master-slice type semiconductor integrated circuit device whose package is a PGA (Pin Grid Array).
2. Description of the Related Art
Hitherto, master-slice type semiconductor integrated circuit devices as a semi-custom products mounting PGA packages have been known.
There are a variety of types of such known master-slice type semiconductor integrated circuit devices. For instance, devices have been known in which all the signal pins of the PGA package are used as input/output pins, as well as devices in which the signal pins on a pair of opposing sides of the PGA are used as input/output signal pins while the signal pins on the other pair of opposing sides of the PGA are exclusively used as input pins. Known master-slice type semiconductor integrated circuit devices also employ a two-layered wiring structure for the PGA as shown in FIGS. 1A and 1B. In this structure, in order to equalize the voltage drops of signals on all the signal pins caused by the resistances of the wires 1, 2 in the package 10, the widths of the wires are so determined that the wires having greater lengths, i.e., the signal lines connected to the pins which are remoter from the center of the package, have greater widths, thus equalizing the resistances of tile wires 1, 2 connected to all signal pins.
The known master-slice type semiconductor integrated circuit device of the type described encounters with a problem in that a large crosstalk noise is generated in the wires connected to the pins which are remotest from the center of the package (referred to as "outermost pins") as compared with the wires connected to the pins closest to the center of the package (referred to as "innermost pins"). This is partly because the pitch of the wires connected to the outermost pins is small due to large widths of these wires and partly because the lengths of these wires are long.
In these known master-slice type semiconductor integrated circuit device, there is a possibility that the output signals are equally allocated to all the signal pins including the pins remoter from the package center and the pins closer to the package pins. If output signals are allocated to the outermost pins aid if these output signals are generated concurrently, very large crosstalk noises are generated in the wires connected to these pins, resulting in a risk of malfunction of an annexed device.